This invention relates generally to a variable frequency signal generating method, and more particularly to a method of generating a variable frequency output signal using a DDS type variable frequency signal generator such that the output signal has no jitter regardless of the oscillation frequency.
A variable frequency signal generator is used in many kinds of fields, such as testing electronic equipment. It is very convenient if the frequency of the output signal can be controlled digitally, because a computer can then be used to control the frequency.
A conventional signal generator whose output frequency is controlled in a digital manner is the DDS (Direct Digital Synthesis) system that is discussed, for example, in U.S. Pat. No. 4,605,868. An advantage of the DDS type signal generator is that it is able to generate any desired waveform. The conventional DDS type variable frequency signal generator will be described hereinafter by reference to FIG. 6.
A clock generator (clock generation means) 10 generates a clock signal having a predetermined frequency and applies it to the clock terminal of an adder 12. A controller (control means) 14, which comprises a microprocessor, a read only memory (ROM) storing a program, and a random access memory (RAM) as a temporary memory, stores in a memory 16, such as a RAM, digital data corresponding to sample amplitudes of a desired waveform output signal. In addition, the controller 14 calculates an address interval value in accordance with a desired output signal frequency, the waveform data (digital data) stored in the memory 16 and the oscillation frequency of the clock generator 10 and applies the calculated address interval value to a latch circuit 18. The digital adder 12 is initially reset and generates an output corresponding to zero. After that, the adder 12 adds the address interval value from the latch circuit 18 and its own previous output value in order to form an address value to address the memory 16. Thus, the digital data value stored in the addressed location may be read out from the memory 16. As discussed hereinbefore, the adder 12 operates as address data generation means. The digital data from the memory 16 is converted into an analog signal by a digital-to-analog (D/A) converter 20 and filtered by a filter 22 to generate an output signal.
Operation of FIG. 6 will be described hereinafter by reference to FIGS. 3 through 5. In order to simplify the explanation of this operation, it is assumed that the memory 16 has sixteen addressable memory locations, having the addresses 0 through 15 in the decimal system (0000 through 1111 in the binary system) and the output signal waveform is a square waveform whose amplitude is 0 or 1. In this specification, the values of the digital data are generally represented in the decimal system. In this instance, the controller 14 stores the digital data in the memory 16 such that the digital data value 0 is stored in the address locations 0 through 7 and the digital data value 1 is stored in the address locations 8 through 15 as shown in FIG. 3. The adder 12 is a four-bit full adder, having four output terminals. The output data value of the adder therefore returns to 0 after reaching 15. The adder also has a carry-in terminal and a carry-out terminal, which are not used and therefore are not shown.
The controller 14 causes the latch circuit 18 to latch an address interval value that is determined in accordance with the clock frequency and the desired frequency of the output signal. First, when the address interval value is assumed to be set to one, the adder 12 increments its digital output signal by one every clock after being reset. Thus, the adder 12 generates the output signal 0, 1, 2, 3, . . . , 14, 15, 0, 1, 2, 3, . . . in this sequence, and the memory 16 is read out with the address interval value of one. The digital data is read from the memory 16, and the D/A converter 20 and the filter 22 convert the data to a pulse signal having the waveform B shown in FIG. 4. This operation is shown in FIG. 4. In FIG. 4, the waveform CLK1 represents the clock signal from the clock generator 10 and the waveform A represents the output signal. If the clock frequency were 250 MHz, the frequency of the output signal would be 15.625 MHz. Numerals written near the output signal waveform represent the output digital value from the adder 12, i.e. the address location of the memory 16 from which the data is read.
When the desired output signal frequency of the DDS type signal generator is twice the frequency of the signal represented by the waveform A, the latch circuit 18 latches the address interval value two from the controller 14. The adder 12 then generates the digital values 0, 2, 4, 6, . . . , 12, 14, 0, 2, . . . in this sequence and the filter 22 produces the output signal waveform B in FIG. 4. For a clock frequency of 250 MHz, the frequency of the output signal would be 31.25 MHz.
If the latch circuit 18 latches the address interval value three from the controller 14, the adder 12 generates the digital values 0, 3, 6, 9, 12, 15, 2, 5, 8, 11, 14, 1, 4, 7, 10, 13, 0, . . . in this sequence and the waveform C of FIG. 4 is obtained as the output signal from the filter 22. In waveform C, the low and high level intervals between the first and second positive going transitions are each,three clock periods, between the second land third positive going transitions the low level interval is two clock periods and the high level interval is three clock periods, and between the third and fourth positive going transitions the low level interval is three clock periods and the high level interval is two clock periods. In other words, the duration of the transition interval (the interval between the time at which the waveform has a first transition from a first nominal state to a second nominal state and a later time at which it has a second transition from the first nominal state to the second nominal state) is not uniform. The output signal is subject to jitter (defined herein as the condition in which the transition interval of the output signal is not uniform) such that for a clock frequency of 250 MHz, the duration of the transition interval varies between 20 ns and 24 ns and has a mean value of 21.33 ns, corresponding to an average frequency of 46.875 MHz. When such a waveform is displayed using an oscilloscope, the waveform may be displayed as shown in FIG. 5 if the trigger slope is +.
This jitter occurs because the transitions contain frequency components at more than twice the clock frequency, and accordingly the Nyquist theorem is not satisfied, and the address interval value is not in an integer relationship to the number of memory locations in the memory 16. Such jitter may occur in output signals having other waveforms, e.g., a fast transition portion of a sawtooth waveform as well as the square waveform.
What is desired to provide a variable frequency signal generating method that is free from the jitter that occurs when the address interval value is not in an integer relationship to the number of memory locations in the memory.